Cadence has announced that the company has expanded its Flash IP offering to include support for the Open NAND Flash Interface (ONFI) 3.0 specification.
The design of high-performance computing platforms, such as solid state drives and enterprise storage solutions; and consumer devices, such as tablets and smartphones that integrate NAND Flash memory are simplified by the ONFI 3 specification.
The new specification defines speeds of up to 400 mega-transfers per second. The Cadence Flash and controller IP also support the Toggle 2.0 specification in addition to the new ONFI 3 specification, the company stated in a press release.
“System designers today see memory as a primary bandwidth bottleneck, which has given rise to many new interface standards intended to simplify design and improve overall system throughput,” said Vishal Kapoor, vice president of Product Marketing, SoC Realization at Cadence. “As the leading supplier of memory and storage IP, Cadence applies its expertise in memory subsystem design to rapidly deliver solutions supporting the latest standards, and to implement those solutions with a highly efficient architecture designed for maximum performance.”
Offering significantly improved system performance when dealing with multiple flash devices, as has become common in high-end mobile devices and SSDs, the Cadence controller and PHY IP implement advanced capabilities of the standard including chip-enable interleaving.
As a result, the IP can deliver up to 95 percent of a NAND device's theoretical maximum throughput. To further enhance performance and deliver enterprise class reliability, Cadence implements sophisticated, highly configurable error correction techniques.
Recently, Panasonic (News - Alert) Corporation deployed the Cadence Palladium XP Verification Computing Platform, as part of the Cadence System Development Suite to ramp up the design time for Systems-on-Chip (SoC) solutions that are created for next-generation digital consumer products such as smart TVs and video recorders.
Panasonic was able to test complex functions and verify hardware-software integration using Palladium XP. Providing graphic validation capabilities of both hardware and software.
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Raju Shanbhag is a contributing editor for TMCnet. To read more of Raju’s articles, please visit his columnist page.
Edited by Jennifer Russell